Typical integrated memory devices include arrays of memory cells arranged in rows and columns. In many such memory devices, several redundant rows and columns are provided to replace malfunctioning memory cells found during testing. Testing is typically performed by having predetermined data values written to selected row and column addresses that correspond to memory cells. The memory cells are then read to determine if the data read matches the data written to those memory cells. If the read data does not match the written data, then those memory cells are likely to contain defects which will prevent proper operation of the memory device.
The defective memory cells may be replaced by enabling the redundant circuitry. A malfunctioning memory cell in a column or a row is substituted with a corresponding redundant element, such as an entire column or row of redundant memory cells, respectively. Therefore, a memory device need not be discarded even though it contains defective memory cells. Substitution of one of the redundant rows or columns is accomplished in a memory device by programming a specific combination of fuses, or if the memory device uses antifuses, by programming a specific combination of antifuses, located in one of several fuse or antifuses circuits in the memory device. Conventional fuses are resistive devices which may be opened or broken with a laser beam or an electric current. Antifuses are capacitive devices that may be closed or blown by breaking down a dielectric layer in the antifuse with a relatively high voltage. A set of fuses or antifuses is associated with each redundant element, and is programmed, or “blown,” according to the address of the defective element the redundant element will replace.
When a row or column address received by the memory device matches one of the programmed addresses, the redundant element associated with the matching address is accessed instead of the row or column having the defective memory cells. In determining whether an address received by the memory device matches one of the programmed addresses, each incoming address is compared to the addresses programmed in the fuse or antifuse circuits. If a match is detected, then the corresponding redundant row or column is accessed, and the defective row or column is ignored, thus, remapping the memory address to the redundant element.
One conventional redundancy system is referred to as a “match and replace” redundancy system. In this system, the addresses of defective rows or columns of memory are programmed in antifuse banks, as previously described, and every address received by the memory device is compared with the programmed addresses. When one of the addresses is received by an address decoder, such as a column address received by a column address decoder, the column address is initially compared with the column addresses programmed in the antifuses. During this time, the column decoder is also decoding the column address in preparation to activate the original column of memory in the event the column address does not match one of the programmed column addresses (i.e., the current column address does not correspond to a defective column of memory). If, however, the column address matches one of the programmed column addresses, the defective column of memory corresponding to the column address is disabled and a redundant column that has been programmed to replace the defective column of memory is activated.
In a match and replace redundancy system, redundant column memory and original column memory are typically associated with a common input/output (“I/O”) path. A time delay is added to every access operation in order to provide sufficient time to compare a current column address with the programmed addresses and determine if there is an address match. More importantly, if an address match is determined, there must be sufficient time to disable the defective column before activating the redundant column of memory. Without the time delay, if a current column address matches one of the programmed column addresses, the defective original column of memory corresponding to the current column address and the redundant column of memory replacing the defective column of memory would both be activated, causing the memory device to malfunction. Although the conventional match and replace redundancy system is simple to design and implement, the system presents a timing disadvantage by having a time delay added to every memory access operation. Where it is desirable for a memory device to provide data with relatively fast access times, the additional time delay added to each memory access may be unacceptable.
One approach that has been developed to avoid the time delay of the conventional match and replace redundancy system is referred to as an I/O multiplexing redundancy system. The I/O multiplexing redundancy system includes redundant memory, such as redundant column memory, for each “redundancy plane.” However, a dedicated set of I/O lines is included for each of the associated redundant memory in addition to the I/O lines for the array of normal memory of a redundancy plane. As with the conventional match and replace redundancy system, the addresses corresponding to defective columns of memory are programmed in antifuse banks. The time delay is avoided by having both the normal column of memory and the redundant column of memory corresponding to a current column address coupled respective sets of I/O lines. The two sets of I/O lines are provided to a multiplexer that is used to select which set of I/O lines to use to couple to an I/O bus. Where a defective column of memory has been remapped to a redundant column of memory, a column address decoder controls the multiplexer to couple the set of I/O lines dedicated to the redundant memory to the I/O bus. The set of I/O lines for the normal memory array, in contrast, are ignored and are not coupled to the I/O bus. By the time each of the columns of the normal memory array and the redundant memory are coupled to the respective sets of I/O lines, the multiplexer has already, or immediately thereafter, coupled the appropriate set of I/O lines to the I/O bus. As a result, a time delay is unnecessary for every access operation. Additionally, the I/O lines for the redundant columns of memory can have less loading, and consequently, the redundant columns of memory may be activated later than the normal columns of memory and still provide data to the multiplexer in time to avoid any additional delays.
Although the I/O multiplexing redundancy system eliminates the need for including a time delay, the extra set of I/O lines requires considerable space on the semiconductor die on which the memory device is formed. As previously discussed, a set of I/O lines are provided for each array of redundant memory associated with a redundancy plane. Typically, a redundancy plane is related to the data prefetch architecture of a memory device, with each data prefetch region of the memory array having its own set of redundancy memory. As memory devices evolve to data prefetch architectures having greater data prefetch numbers in order to improve output data bandwidth, using an I/O multiplexing redundancy system will require a greater number of additional I/O lines and consequently, require more space on the semiconductor die. Where space on the semiconductor die on which the memory device is formed, use of the I/O multiplexing redundancy scheme is undesirable. Additionally, the use of an I/O multiplexing redundancy system for memory devices having greater data prefetch architectures is not practical in such circumstances.
Another redundancy system that has been developed to reduce or eliminate the time delay of conventional match and replace redundancy system utilizes redundant elements physically located at the periphery of a redundancy domain that are utilized by “shifting” the decoding of memory addresses “up” or “down” to avoid defective memory elements. A redundancy domain includes a limited number of redundancy elements allocated for the defective memory of a region of memory. For example, with respect to column redundancy, when a defective column of memory is identified, the defective column is ignored by shifting all of the column addresses over by one column, and utilizing a column of redundant memory at the periphery. Thus, the address of the defective column is now remapped to an adjacent column of memory. Shortcomings of this redundancy system include sacrificing considerable space on the die of the memory device to include the logic circuits and address decoding circuitry necessary to remap shifted memory addresses. Additionally, this redundancy system lacks flexibility because the allocation of redundant elements for each redundancy domain is limited by the complexity of the supporting logic. Including more redundant column memory to improve flexibility is an undesirable option as well since this results in the complexity and size of the column decoders to increase significantly.
Therefore, there is a need for an alternative redundancy system that provides flexibility in design and can be practically implemented in current and later memory device architectures.